Among technologies which the present inventors have studied, the following technology can be considered to be relevant to a semiconductor device including a phase change memory, for example.
The memory device uses, as material of a storage layer, chalcogenide material (or phase change material), such as a Ge—Sb—Te system, an Ag—In—Sb—Te system, etc. which include antimony (Sb) and tellurium (Te) at least. The property of the phase change memory using chalcogenide material is described in Non-patent Document 1, for example.
FIG. 2 is a drawing illustrating the relationship between temperature and a pulse width necessary for phase change to take place in a resistive memory device using the phase change material. When storage data ‘0’ is written in the present memory device, a reset pulse is applied, which heats the element more than the melting point Ta of the chalcogenide material and cools it down rapidly, as illustrated in FIG. 2. By shortening the reset pulse to keep the given total energy small and setting the cool-down time t1 as narrow as about 1 ns, for example, the chalcogenide material changes to the amorphous state with high resistance.
On the contrary, when storage data ‘1’ is written, by applying a set pulse which maintains the memory device in a temperature range lower than the melting point Ta and higher than the crystallization temperature Tx which is equal to or higher than the glass-transition temperature, the chalcogenide material changes to the polycrystalline state with low resistance. Time t2 required for crystallization changes with composition of the chalcogenide material. The temperature of the element, illustrated in FIG. 2, depends on the Joule's heat which the memory device itself generates, and the thermal diffusion to the environment.
Patent Document 1 describes a specific method to write storage data ‘1.’ FIG. 3 illustrates a cell current pulse used for the set operation, and FIG. 4 illustrates wave-shaping circuitry used to generate the cell current pulse. In FIG. 3, a level 122 denotes a cell current amplitude at which the resistive memory device can be phase-changed to a high resistance (reset) state. By lowering the cell current amplitude gradually from the level 122 toward a low level 130, the resistive memory device is phase-changed to a low resistance (set) state. In the wave-shaping circuitry illustrated in FIG. 4, a symbol 203 denotes a power supply voltage, a symbol 205 denotes a ground voltage, a symbol 204 denotes a current source, a symbol 208 denotes a transistor used for a cell select switch, and a symbol 108 denotes a resistive memory device. Symbols 210_1-210_K denote switching transistors, and symbols 212_1-212_K denote current sources. By activating the switching transistor 208, the current of level 122 in FIG. 3 is applied to the memory device. By activating control signals C1-CK in sequence, and conducting the corresponding switching transistors 210_1-210_K, the current applied to the memory device is reduced gradually. The use of such a cell current pulse allows to shorten the fall time to about 200 ns and to shorten the set time.
Non-Patent Document 2 describes the architecture with respect to an interface (I/F) for reducing a programming current. To be specific, the programming current control of a memory chip is realized by stopping a power circuit for programming drivers, according to the number of bits to be programmed at the same time.    [Patent Document 1] U.S. Pat. No. 6,487,113    [Non-patent Document 1) IEEE International Electron Devices meeting, TECHNICAL DIGEST, (U.S.A.), 2001, pp. 803-806    [Non-patent Document 2) IEEE International Solid-State Circuits Conference, Digest of Technical Papers, (U.S.A.), 2006, pp. 140-141